The present invention relates to a semiconductor device for rectifying aimed for high withstand voltage including principally a pn junction. More specifically, the present invention relates to a semiconductor device for rectifying for making forward voltage drop small as well as making switching speed (reverse recovery time, Trr) fast, still maintaining high withstand voltage.
The conventional semiconductor devices for rectifying are classified into the pn junction structure type and the Schottky barrier structure type (hereinafter referred to as SBD). The pn junction type one has characteristics in which although forward voltage drop is large, the structure is hard to be broken also against the reverse direction high voltage, so, consequently, this type is used for high withstand voltage use. The SBD type one has characteristics in which although this type is not suitable for high withstand voltage use, particularly forward voltage drop is small as well as switching time Trr is fast, so, this type is used effectively for also high frequency circuits and so on.
The conventional diode for rectifying including a pn junction structure is constructed as shown in, for example, FIG. 8. Referring to FIG. 8, reference numeral 21 denotes an n+-type semiconductor substrate, on which an nxe2x88x92-type epitaxial growth layer 22 is formed to a thickness of, for example, approximately 50 micrometers; and p+-type diffusion region 23 is provided into the surface portion of the epitaxial growth layer 22, to a depth of, for example, approximately 20 micrometers forming a pn junction with the epitaxial growth layer 22. Around the pn junction, p-type FLRs 24 are provided for improving high withstand voltage in the transverse direction. For such use in which the withstand voltage is greater than, for example, approximately 500 volts, in the semiconductor device for rectifying including a pn junction structure, the thickness d of the epitaxial growth layer 22 in the bottom portion of the p+-type diffusion region 23 is formed to be thicker so that the thickness d is greater than 50 micrometers. Reference numeral 125 denotes an insulator film, 26 and 27 denote a p-side electrode and an n-side electrode, respectively, each made of Ag, Al or the like.
In this semiconductor device for rectifying including a pn junction type, when operation is made to be off (that is, the applied voltage is in the reverse direction), unless positive holes, which are minority carriers injected in the nxe2x88x92-type epitaxial growth layer 22, disappear immediately, electric current flow does not become zero and then the switching speed becomes slow. For the reason mentioned above, in the conventional art, a countermeasure is adopted in which a heavy metallic material such as, for example, Au or the like is diffused in advance in the epitaxial growth layer 22 so that minority carriers can be trapped easily to make the switching speed fast. As shown in FIG. 9, diffusing a heavy metallic material is preferable because the smaller the switching speed Trr is made to be when the more doping amount is increased. However, since electric resistance in the epitaxial growth layer 22 is more increased, when such a heavy metallic material is diffused, as shown in FIG. 9, when the more doping amount of such a heavy metal is increased, the larger forward voltage drop VF becomes and the doping amount is in trade off relation with switching speed. Therefore, switching speed Trr can not be made to be sufficiently fast. In addition, although not illustrated, the more doping amount of a heavy metal is increased, the more leakage of electric current is increased.
On the other hand, for the purpose of improving withstand voltage in the SBD structure, as disclosed in Japanese Patent Publication Tokko-Sho59-35183 or as shown in FIG. 10(a), there proposed a structure in which a p+-type region 28 is formed in an island like shape or a stripe shape in the nxe2x88x92-type epitaxial growth layer 22, and a depletion layer formed in the epitaxial growth layer side sandwiched between the p+-type regions 28 reduces the reverse direction leakage current, so that the withstand voltage is enhanced. However, in this structure, the principal part of the structure is the Schottky barrier junction and then the area of the SBD portion is more than half of the layer. In addition, in FIG. 10(a), an identical portion is referred as the same reference numeral in FIG. 8. Reference numeral 29 denotes an electrode forming Schottky junction between the epitaxial growth layer and the electrode itself.
In addition, as disclosed in, for example, Japanese Published Unexamined Patent Publication Tokkai-Hei7-226521, there proposed a structure in which both a Schottky junction and a pn junction are arranged in parallel in the semiconductor body so that the each preferable characteristics is incorporated simultaneously thereto with the ratio of each being nearly the same; the surface side of the pxe2x88x92-type region is made to be p+-type region so that the amount of the carrier injection to the underside of the Schottky barrier junction is made to be increased; and minority carriers remaining in nxe2x88x92-type region are made to disappear rapidly. Further, the ratio, which is disclosed in the above publication, between the Schottky junction and the pn junction is exemplified as follows: Wp representing the width of the pn junction to be 15 micrometers and WN representing the width of the Schottky barrier portion to be 5 micrometers (WP:WN=3:1); as shown in FIG. 10(b), the ratio of the area Q of Schottky barrier portion to the area P of the pn juntion portion is as follows: {13xc3x9713xe2x88x923xc3x973xc3x979(pieces)}:{3xc3x973xc3x979(pieces)}=88:81=1.09:1; and the ratio of each region nearly equals to each other.
As mentioned above, for the purpose of enhancing withstand voltage in Schottky barrier semiconductor device, the structure in which a pn junction is provided in an island like shape or a stripe shape in semiconductor layers where Schottky junction is provided, so that both a Schottky junction and a pn junction are arranged in parallel is well-known. However, for the purpose of obtaining a semiconductor device for rectifying, especially for super high withstand voltage, for example, from not less than 200 volts to approximately 1700 volts, unless making the thickness d of the epitaxial layer shown in FIG. 8 or FIG. 10 to be thicker, sufficient withstand voltage cannot be obtained. If the distance d is large, series resistance in the SBD portion becomes large and the influence upon forward voltage drop becomes remarkable. Thus, there arises a problem where a semiconductor device for rectifying aimed for high withstand voltage in which forward voltage drop is made to be small and switching time is made to be fast is not obtained.
The present invention is achieved in order to solve the above mentioned problem. The purpose of the present invention is to provide a semiconductor device for rectifying having pn junction in which high withstand voltage is still maintained and, further, switching speed is fast through making minority carriers remaining in semiconductor layers disappear immediately in the transient period in which operation is made to be off(forward direction potential is changed to reverse direction potential).
The semiconductor device for rectifying of the present invention comprises: a semiconductor substrate of a first conductivity type with a high impurity concentration;
a semiconductor layer of the first conductivity type with a low impurity concentration formed by epitaxial growth on the semiconductor substrate;
a plurality of semiconductor regions of a second conductivity type formed in a surface side of the semiconductor layer; and
a metal layer formed on a surface of the semiconductor layer and on a surface of the semiconductor regions, the metal layer forming a Schottky barrier with the semiconductor layer,
wherein the semiconductor regions are formed to be regularly arranged in such a manner that a plan configuration of each of the semiconductor regions on a surface of the semiconductor layer is a circularity or a polygon, and that a portion which is the furthest from a center portion of the circularity or polygon neighbors or overlaps with the circularity or polygon of an immediate adjacent semiconductor region.
Hereinafter, expression xe2x80x9ccircularityxe2x80x9d or xe2x80x9cpolygonxe2x80x9d shape includes not only a perfect circularity or a quadrilateral but a shape including a straight portion and arc portion, or an ellipse shape or the like; expression xe2x80x9cpolygonxe2x80x9d shape means that the number of angles is not less than four. In addition, a portion which is the furthest from the center portion (the furthest portion) means a portion on a rim in the case of a circularity and means a corner portion in the case of a polygon. Further, in expression xe2x80x9cneighbor or overlapxe2x80x9d means that it is not necessary that the furthest portions of both two immediate adjacent semiconductor regions neighbor or overlap each other, but the following case is also included: the furthest portion of one of the semiconductor region neighbors or overlaps with the other portion except for the furthest portion of the other semiconductor region.
Adoption of such structure allows to form a rectifying device for high withstand voltage having a pn junction, because the metal layer is contacted in the second conductivity semiconductor regions with an ohmic contact. Specifically, around the second conductivity type semiconductor regions, a first conductivity type semiconductor layer lies in a position which is apart nearly equivalent distance from the center portion, and Schottky junction is formed between the first conductivity type semiconductor layer and the metal layer. In this Schottky junction, movement of electrons only is carried out, but movement of holes is not carried out. Thus, when operation is changed to the reverse direction, even in a case where the minority carriers(holes) exist in the first conductivity type semiconductor layer, electrons can act so that the minority carriers (positive holes) become to disappear. As the result, switching speed can be made to be fast. Furthermore, the Schottky junction is required to have only electrons supplying function for supplying electrons to the semiconductor layer around the pn junction in order to make the minority carriers (holes) disappear when operation is off, and the Schottky junction portion is not required to have a function as a Schottky diode, and the Schottky junction may be provided around the second conductivity type regions. Therefore, the Schottky junction can be constructed with sufficiently small area, so there is not arising the forward voltage drop, even in a case where the first conductivity type semiconductor layer is thick by being used for high withstand voltage.
When the semiconductor regions are formed to be arranged so that a total area of the semiconductor regions on a surface of the semiconductor layer is between not less than two times and not more than six times an area of remaining surface of the semiconductor layer on which the semiconductor regions are not formed, the minority carriers are made to disappear without making the forward voltage drop large. Such division into the above mentioned ratio of area can provide similar advantages, even in a case where the shape of the semiconductor regions is not the same as the above mentioned shape.
Specifically, the semiconductor regions are formed so that a plan configuration of each of the semiconductor regions on a surface of the semiconductor layer is a circularity, and that periphery portions of the circularity of each of immediate adjacent semiconductor regions are in contact each other; alternatively, the semiconductor regions are formed so that a plan configuration of each of the semiconductor regions on a surface of the semiconductor layer is a circularity, and that periphery portions of the circularity of each of immediate adjacent semiconductor regions overlap each other; alternatively, the semiconductor regions are formed so that a plan configuration of each of the semiconductor regions on a surface of the semiconductor layer is a rhombus, and that corner portions of the rhombus of each of immediate adjacent semiconductor regions overlap each other; alternatively, the semiconductor regions are formed so that a plan configuration of each of the semiconductor regions on a surface of the semiconductor layer is an octagon, and that corner portions of the octagon of each of immediate adjacent semiconductor regions overlap each other; alternatively, the semiconductor regions are formed to be regurally arranged so that a plan configuration of each of the semiconductor regions on a surface of the semiconductor layer is a hexagon and the hexagon of each of the arranged semiconductor regions is rotated by 90 degrees in order, and that a corner portion and one side portion of the hexagon of each of immediate adjacent semiconductor regions overlap each other.
When a thickness of the semiconductor layer formed by epitaxial growth is not less than 20 micrometers, a withstand voltage for not less than 200 volts can be obtained without bringing influence of the forward voltage drop.